feat: xHCI endpoint matching, EP0 GET_REPORT, MSI hardening#238
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feat: xHCI endpoint matching, EP0 GET_REPORT, MSI hardening#238
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…SI hardening Major xHCI driver overhaul to match Linux's exact initialization sequence on Parallels ARM64 virtual xHC (NEC uPD720200). Key changes: - Batch ConfigureEndpoint with all endpoints in single command (matches Linux) - Drop+Add toggle reset per endpoint after initial ConfigureEndpoint - Full 32-byte Slot Context copy matching Linux xhci_slot_copy - Mult=0 for non-isochronous endpoints per xHCI spec §6.2.3 - EP0 GET_REPORT polling for keyboard input (working at 4Hz) - Deferred TRB queueing after SPI enable to avoid race conditions - GIC DSB+ISB barriers on SPI enable/disable to prevent MSI storms - Comprehensive heartbeat diagnostics for xHCI state monitoring - USB descriptor additions: BOS, SET_INTERFACE, SET_ISOCH_DELAY, SET_REPORT - MAX_SLOTS increased to 32 to match Linux CONFIG value - .gitignore: exclude esp/ build artifact and debug capture files Interrupt endpoint transfers still return CC=12 (Endpoint Not Enabled), investigation ongoing. EP0 control transfers work correctly. Co-Authored-By: Ryan Breen <rbreen@gmail.com> Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Summary
xhci_check_bandwidth+xhci_endpoint_resetflowChanges
kernel/src/drivers/usb/xhci.rs: Major rewrite — batch endpoint config, Drop+Add reset, EP0 polling, deferred TRB queueing, endpoint state diagnosticskernel/src/arch_impl/aarch64/gic.rs: DSB+ISB barriers on SPI enable/disablekernel/src/arch_impl/aarch64/timer_interrupt.rs: Extended heartbeat with xHCI transfer/error/doorbell/endpoint diagnosticskernel/src/drivers/usb/descriptors.rs: BOS descriptor type, SET_INTERFACE, SET_ISOCH_DELAY, SET_REPORT requestskernel/src/drivers/mod.rs: Raw serial debug breadcrumbs for xHCI init path.gitignore: Excludeesp/build artifact and debug capture filesStatus
Interrupt endpoint transfers still return CC=12 (Endpoint Not Enabled) on the Parallels virtual xHC despite endpoint contexts matching Linux byte-for-byte. EP0 control transfers work correctly. Investigation ongoing.
Test plan
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