JTAG Controller for Memory Access

Overview

This project implements a JTAG TAP controller and a programming interface for memory access. It provides synthesizable SystemVerilog modules and example testbenches for both Verilator and SystemVerilog commercial simulators.

Features

• JTAG TAP controller with IR/DR scan
• Programming controller for memory read/write via JTAG
• CDC modules for safe signal transfer between JTAG and system clocks
• Example testbenches (SystemVerilog and C++)

Directory Structure

• src — Main SystemVerilog source files
• verilator — Verilator C++ testbench and Makefile
• xcelium — SystemVerilog testbench for commercial simulators
• README.md — This file

How It Works

• The JTAG TAP controller receives instructions and data via the JTAG interface.

• The programming controller decodes JTAG commands and accesses memory accordingly.

• All signals crossing between JTAG and system clocks are synchronized using CDC modules.

• During read and write operations, the memory must be isolated from the rest of the system using the mem_control_enable signal, which is asserted by the programming controller (see Programming_interface.sv and example TOP.sv module). This signal should control multiplexers on the memory's input and output ports to ensure safe access during JTAG operations.

  

  Figure: JTAG interface for memory access

JTAG Instructions

• NOP (0x0): No operation
• MEM_CTRL (0x1): Isolate memory from CPU for safe programming
• WRITE (0x2): Write data to memory
• READ (0x3): Read data from memory
• DONE (0x4): Close JTAG interface and reset CPU

Running the Testbench

Verilator (C++ testbench)

Requires Verilator and GTKWave. Use the Makefile with the run target to start the simulation and the waves target to visualize the waveform file using GTKWave.

make -C tb/verilator run
make tb/verilator waves

SystemVerilog (Xcelium or similar)

The makefile includes commands to launch Cadence Xcelium. Use the same targets as the Verilator makefile.

make run
make waves

Customization

• Change memory/data width by editing parameters in Programming_interface.sv and testbenches.
• Add new JTAG instructions by extending the IR decode logic and testbenches.