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Preethigrace-7/README.md

Hi there 👋

I’m currently exploring opportunities in the VLSI field. Passionate about digital design, RTL, and ASIC flow.

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  1. VSD-Digital-VLSI-SoC-Design-and-Planning VSD-Digital-VLSI-SoC-Design-and-Planning Public

    This repository serves as a comprehensive documentation of my learnings from the Digital VLSI SoC Design and Planning course offered by VLSI System Design (VSD) under the NASSCOM-VSD Program.

  2. 6TSRAM 6TSRAM Public

    Simulation files and documentation for the Energy-Efficient 6T SRAM Cell Design project, created for the Ratan Tata Tribute Circuit Design & Simulation Hackathon, focusing on a low-power 130nm SRAM…

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  3. HDLBits_Solutions HDLBits_Solutions Public

    Verilog 1

  4. RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR Public

    Build up myself with extendable knowledge from Fundamentals of VLSI to Chip Tapeout. Worked on RISCV 32bit processor from RTL to GDSII flow with specified Industry standard constraints using Open s…

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