I’m currently exploring opportunities in the VLSI field. Passionate about digital design, RTL, and ASIC flow.
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VSD-Digital-VLSI-SoC-Design-and-Planning
VSD-Digital-VLSI-SoC-Design-and-Planning PublicThis repository serves as a comprehensive documentation of my learnings from the Digital VLSI SoC Design and Planning course offered by VLSI System Design (VSD) under the NASSCOM-VSD Program.
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RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR
RTL-TO-GDSII-FLOW-OF-RISC_V-32-BIT-PROCESSOR PublicBuild up myself with extendable knowledge from Fundamentals of VLSI to Chip Tapeout. Worked on RISCV 32bit processor from RTL to GDSII flow with specified Industry standard constraints using Open s…
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