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Pull requests: OpenXiangShan/XiangShan
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fix(CtrlBlock): typo in comment, 'disble' to 'disable'
#5361
opened Dec 13, 2025 by
Kingfish404
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chore(perf-ci): reorganize perf ci scripts and add custom test options
#5360
opened Dec 13, 2025 by
Yan-Muzi
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ci(perf): synchronise the format of report with env_script
#5359
opened Dec 13, 2025 by
Maxpicca-Li
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feat(bpu): add debug_isRVC in resolve io
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: verification
To make function/performance verification easier
#5355
opened Dec 11, 2025 by
TheKiteRunner24
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perf(StoreQueue): Cbo no longer flush pipe
note: do not merge
(PR) For maintainer: do not merge this pull request yet
fix(pmu): enable ras pmu in bpu
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: verification
To make function/performance verification easier
area(Bpu): move BaseTable from Tage to MainBtb
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: area
To reduce area comsuption
feat(bpu): use abtb result when abtb and ubtb positions match
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: performance
To improve performance
chore(backend): remove some dead code
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: code quality
To make code more readable & maintainable
refactor(MissQueue): Eliminate duplicate logic in multiple functions
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: code quality
To make code more readable & maintainable
feat(prefetch): make the stream prefetcher configurable for training granularity
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5308
opened Dec 4, 2025 by
ywlcode
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feat(utage): add enable signal and MicroTAGE perf counters
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
topic: verification
To make function/performance verification easier
feat(backend): support vec fast wake up
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
#5283
opened Nov 30, 2025 by
sinceforYy
•
Draft
fix(prefetch): prefetch request can be set in pipeline
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5275
opened Nov 28, 2025 by
Maxpicca-Li
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refactor(prefetchmonitor):remove fdpmonitor and fix some statistical bugs
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
refactor(fpuCtrl,i2f):remove redundant fpctrl; i2f use fpPipedFuncUnit
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
feat(sc): sc add bias table and connect it to bp
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
submodule(difftest): refactor DiffTop, PhyReg and Refill
module: tool
difftest, gsim, XSpdb, Makefiles, scripts, etc.
#5221
opened Nov 15, 2025 by
klin02
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doc(readme): add usage info of galaxsim simu
module: documentation
Improvements or additions to documentation
#5214
opened Nov 13, 2025 by
x-epic
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feat(rvv):Add oldvd dependency clearing for some instructions
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
#5212
opened Nov 12, 2025 by
HeiHuDie
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