docs(dn) Tony Korycki 2/22/26

src/design_notebooks/2026spring/ajk8795.md

@@ -5,4 +5,20 @@
 - Found a partner (Gloria) for the RiSC-16 onboarding project and we scheduled our first meeting for Friday 
 - Read the slides fo the onboarding project and the ones from the first in-person meeting
 
-I already had WSL set up and was familiar with using Git so I didnt run into many issues getting started. The website was very clear and easy to follow. 
+I already had WSL set up and was familiar with using Git so I didnt run into many issues getting started. The website was very clear and easy to follow. 
+
+## Week 2: 02/01-02/08/2026
+
+- Went thorough the first week of onboarding - created the PC and Memeory moedules with teammate Gloria. We also mistakenly did the first onboarding lab with CMake. 
+- We added our work to a (github repo)[https://github.com/tonykorycki/risc16-onboarding] and I walked gloria thorugh using git and github to collaborate.
+- Setting up the verilog modules went smoothly cause we already both have experience with verilog. We also set up some testbenches for the modules and tried them out in Icarus Verilog.
+
+
+## Week 3: 02/08-02/15/2026
+
+- We continued working on the onboarding project and added the ALU module and the data memory module. Did not add testbenches for those but again went smoothly.
+- We are still a little confusde about what kind of notes we need to include.
+
+## Week 4: 02/15-02/22/2026
+- We added the register file module and the control unit module. We had some scheduiling issues so we didnt meet and instead worked on the modules separately.
+- Compiled with iverilog and they seem to work. will see once we add testbwnches