docs(dn): Ibrahim Hashim 2/15/2026

src/design_notebooks/2026spring/irh8156.md

@@ -7,4 +7,31 @@ Project Work:
   * Went over onboarding labs 1-4.
 
 Comments:
-  * I created my first design notebook and submitted my first pull request of the semester.
+  * I created my first design notebook and submitted my first pull request of the semester.
+
+
+## Week of 1 Feb 2026
+
+Project Work: 
+ * Made sure I knew and rememebered everything from onboarding labs 1-4. 
+
+
+## Week of 8 Feb 2026
+
+Project Work:
+* Had no assigned work for this week.
+
+
+## Week of 15 Feb 2026
+
+Project Work:
+* Had a team meeting this week,
+* Went over the NYU Processor Design Team SoC CPU Core report
+
+Notes on the report:
+* The overall design of the CPU is a 32 bit CPU using the RISC-V 32 instruction set
+* It has a regular 5 stage pipeline like we took in comparch
+* It uses a 2 bit branch predictor
+* Its data cache is 2 way associative
+* A question I have is if a different type of branch predictor would improve the performance of the CPU, specificially something more advanced, and what tradeoffs implementing something like that would have
+* Why don't we use data forwarding when the hazard detection stalls the pipeline using NOPs?