diff --git a/arch.mk b/arch.mk index fb34653813..bed21b0455 100644 --- a/arch.mk +++ b/arch.mk @@ -618,6 +618,13 @@ ifeq ($(ARCH),PPC) CFLAGS+=-fno-builtin-printf endif + # Target-specific CPU flags + ifeq ($(TARGET),nxp_t2080) + CFLAGS+=-mcpu=e6500 -mno-altivec + else ifeq ($(TARGET),nxp_t1024) + CFLAGS+=-mcpu=e5500 + endif + # Prune unused functions and data CFLAGS+=-ffunction-sections -fdata-sections LDFLAGS+=-Wl,--gc-sections diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index b72bad4042..1edd9f698e 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -101,7 +101,7 @@ #define USE_LONG_JUMP #elif defined(TARGET_nxp_t2080) - /* NXP T0280 */ + /* NXP T2080 */ #define CORE_E6500 #define CPU_NUMCORES 4 #define CORES_PER_CLUSTER 4 @@ -118,13 +118,16 @@ #define ENABLE_L1_CACHE #define ENABLE_L2_CACHE - #define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */ - #define L2SRAM_SIZE (256UL * 1024UL) + #define L2SRAM_ADDR (0xF8F00000UL) /* CPC as SRAM (1MB) */ + #define L2SRAM_SIZE (1024UL * 1024UL) #define INITIAL_SRAM_ADDR L2SRAM_ADDR - #define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB + /* CPC SRAM transactions traverse the CoreNet interconnect, which + * requires a LAW to route them. LAW_TRGT_DDR_1 is used as a routing + * target; the CPC intercepts the transaction before it reaches DDR. */ + #define INITIAL_SRAM_LAW_SZ LAW_SIZE_1MB #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1 - #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K + #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_1M #define ENABLE_INTERRUPTS @@ -285,20 +288,23 @@ #define CPC_BASE (CCSRBAR + 0x10000) /* 8.2 CoreNet Platform Cache (CPC) Memory Map */ #define CPCCSR0 (0x000) + #define CPCEWCR0 (0x010) #define CPCSRCR1 (0x100) #define CPCSRCR0 (0x104) + #define CPCERRDIS (0xE44) #define CPCHDBCR0 (0xF00) #define CPCCSR0_CPCE (0x80000000 >> 0) #define CPCCSR0_CPCPE (0x80000000 >> 1) #define CPCCSR0_CPCFI (0x80000000 >> 10) + #define CPCCSR0_CPCFL (0x80000000 >> 20) #define CPCCSR0_CPCLFC (0x80000000 >> 21) - #define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE) #ifdef CORE_E6500 - #define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 14-15 */ - #define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */ - #define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */ + /* T2080: 2MB CPC, 16 ways, 128KB per way */ + #define CPCSRCR0_SRAMSZ_256 (0x1 << 1) /* ways 14-15, 256KB */ + #define CPCSRCR0_SRAMSZ_1024 (0x3 << 1) /* ways 8-15, 1MB */ + #define CPCSRCR0_SRAMSZ_2048 (0x4 << 1) /* ways 0-15, 2MB */ #else /* CORE E5500 */ #define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 6-7 */ #define CPCSRCR0_SRAMSZ_128 (0x2 << 1) /* ways 4-7 */ @@ -483,13 +489,21 @@ #define SPRN_DBSR 0x130 /* Debug Status Register */ #define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_TSR 0x3D8 /* Timer Status Register */ -#define SPRN_TCR 0x3DA /* Timer Control Register */ +#ifdef CORE_E6500 + #define SPRN_TSR 0x150 /* Timer Status Register (SPR 336) */ + #define SPRN_TCR 0x154 /* Timer Control Register (SPR 340) */ + #define SPRN_DEAR 0x03D /* Data Exception Address Register (SPR 61) */ + #define SPRN_ESR 0x03E /* Exception Syndrome Register (SPR 62) */ +#else + #define SPRN_TSR 0x3D8 /* Timer Status Register */ + #define SPRN_TCR 0x3DA /* Timer Control Register */ + #define SPRN_DEAR 0x3D5 /* Data Exception Address Register */ + #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#endif + #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ #define TCR_DIE 0x04000000 /* Decrement Interrupt Enable */ - -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ #define SPRN_MCSR 0x23C /* Machine Check Syndrome Register */ #define SPRN_PVR 0x11F /* Processor Version */ #define SPRN_SVR 0x3FF /* System Version */ @@ -524,6 +538,8 @@ #define SRR0 0x01A /* Save/Restore Register 0 */ #define SRR1 0x01B /* Save/Restore Register 1 */ +#define SPRN_MCSRR0 0x23A /* Machine Check Save/Restore Register 0 */ +#define SPRN_MCSRR1 0x23B /* Machine Check Save/Restore Register 1 */ #define MSR_DS (1<<4) /* Book E Data address space */ #define MSR_IS (1<<5) /* Book E Instruction address space */ @@ -674,6 +690,31 @@ extern void dcache_disable(void); #else /* Assembly version */ +#ifdef CORE_E6500 +/* e6500 has 64-bit MAS registers - must clear upper 32 bits */ +#define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \ + lis reg, BOOKE_MAS0(tlb, esel, 0)@h; \ + ori reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \ + mtspr MAS0, reg;\ + lis reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@h; \ + ori reg, reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@l; \ + mtspr MAS1, reg; \ + li reg, 0; \ + oris reg, reg, BOOKE_MAS2(epn, winge)@h; \ + ori reg, reg, BOOKE_MAS2(epn, winge)@l; \ + mtspr MAS2, reg; \ + lis reg, BOOKE_MAS3(rpn, 0, perms)@h; \ + ori reg, reg, BOOKE_MAS3(rpn, 0, perms)@l; \ + mtspr MAS3, reg; \ + lis reg, urpn@h; \ + ori reg, reg, urpn@l; \ + mtspr MAS7, reg; \ + isync; \ + msync; \ + tlbwe; \ + isync; +#else +/* e500/e5500 - 32-bit MAS registers */ #define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \ lis reg, BOOKE_MAS0(tlb, esel, 0)@h; \ ori reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \ @@ -694,6 +735,7 @@ extern void dcache_disable(void); msync; \ tlbwe; \ isync; +#endif /* CORE_E6500 */ /* readability helpers for assembly to show register versus decimal */ #define r0 0 diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index 6cc3159791..e5a2272f78 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -23,277 +23,9 @@ #include "printf.h" #include "image.h" /* for RAMFUNCTION */ #include "nxp_ppc.h" +#include "nxp_t2080.h" -/* Tested on T2080E Rev 1.1, e6500 core 2.0, PVR 8040_0120 and SVR 8538_0011 */ - -/* T2080 */ -#define SYS_CLK (600000000) /* 100MHz PLL with 6:1 = 600 MHz */ - -/* T2080 PC16552D Dual UART */ -#define BAUD_RATE 115200 -#define UART_SEL 0 /* select UART 0 or 1 */ - -#define UART_BASE(n) (CCSRBAR + 0x11C500 + (n * 0x1000)) - -#define UART_RBR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */ -#define UART_THR(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */ -#define UART_IER(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */ -#define UART_IIR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */ -#define UART_FCR(n) *((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */ -#define UART_LCR(n) *((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */ -#define UART_MCR(n) *((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */ -#define UART_LSR(n) *((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */ - -/* enabled when UART_LCR_DLAB set */ -#define UART_DLB(n) *((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */ -#define UART_DMB(n) *((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */ - -#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */ -#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */ -#define UART_FCR_FEN (0x01) /* FIFO enable */ -#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */ -#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */ -#define UART_LSR_TEMT (0x40) /* Transmitter empty */ -#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */ - - -/* T2080 IFC (Integrated Flash Controller) - RM 13.3 */ -#define IFC_BASE (CCSRBAR + 0x00124000) -#define IFC_MAX_BANKS 8 - -#define IFC_CSPR_EXT(n) *((volatile uint32_t*)(IFC_BASE + 0x000C + (n * 0xC))) /* Extended Base Address */ -#define IFC_CSPR(n) *((volatile uint32_t*)(IFC_BASE + 0x0010 + (n * 0xC))) /* Chip-select Property */ -#define IFC_AMASK(n) *((volatile uint32_t*)(IFC_BASE + 0x00A0 + (n * 0xC))) -#define IFC_CSOR(n) *((volatile uint32_t*)(IFC_BASE + 0x0130 + (n * 0xC))) -#define IFC_CSOR_EXT(n) *((volatile uint32_t*)(IFC_BASE + 0x0134 + (n * 0xC))) -#define IFC_FTIM0(n) *((volatile uint32_t*)(IFC_BASE + 0x01C0 + (n * 0x30))) -#define IFC_FTIM1(n) *((volatile uint32_t*)(IFC_BASE + 0x01C4 + (n * 0x30))) -#define IFC_FTIM2(n) *((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30))) -#define IFC_FTIM3(n) *((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30))) - -#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFF0000) /* Physical base address */ -#define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */ -#define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */ -#define IFC_CSPR_WP 0x00000040 /* Write Protect */ -#define IFC_CSPR_MSEL_NOR 0x00000000 /* Mode Select - NOR */ -#define IFC_CSPR_MSEL_NAND 0x00000002 /* Mode Select - NAND */ -#define IFC_CSPR_MSEL_GPCM 0x00000004 /* Mode Select - GPCM (General-purpose chip-select machine) */ -#define IFC_CSPR_V 0x00000001 /* Bank Valid */ - -/* NOR Timings (IFC clocks) */ -#define IFC_FTIM0_NOR_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */ -#define IFC_FTIM0_NOR_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */ -#define IFC_FTIM0_NOR_TAVDS(n) (((n) & 0x3F) << 8) /* Delay between CS assertion */ -#define IFC_FTIM0_NOR_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */ -#define IFC_FTIM1_NOR_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */ -#define IFC_FTIM1_NOR_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */ -#define IFC_FTIM1_NOR_TSEQ(n) (((n) & 0x3F) << 0) /* sequential read access delay */ -#define IFC_FTIM2_NOR_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */ -#define IFC_FTIM2_NOR_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */ -#define IFC_FTIM2_NOR_TWPH(n) (((n) & 0x3F) << 10) /* Chip-select hold time */ -#define IFC_FTIM2_NOR_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */ - -/* GPCM Timings (IFC clocks) */ -#define IFC_FTIM0_GPCM_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */ -#define IFC_FTIM0_GPCM_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */ -#define IFC_FTIM0_GPCM_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */ -#define IFC_FTIM1_GPCM_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */ -#define IFC_FTIM1_GPCM_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */ -#define IFC_FTIM2_GPCM_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */ -#define IFC_FTIM2_GPCM_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */ -#define IFC_FTIM2_GPCM_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */ - -/* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */ -enum ifc_amask_sizes { - IFC_AMASK_64KB = 0xFFFF0000, - IFC_AMASK_128KB = 0xFFFE0000, - IFC_AMASK_256KB = 0xFFFC0000, - IFC_AMASK_512KB = 0xFFF80000, - IFC_AMASK_1MB = 0xFFF00000, - IFC_AMASK_2MB = 0xFFE00000, - IFC_AMASK_4MB = 0xFFC00000, - IFC_AMASK_8MB = 0xFF800000, - IFC_AMASK_16MB = 0xFF000000, - IFC_AMASK_32MB = 0xFE000000, - IFC_AMASK_64MB = 0xFC000000, - IFC_AMASK_128MB = 0xF8000000, - IFC_AMASK_256MB = 0xF0000000, - IFC_AMASK_512MB = 0xE0000000, - IFC_AMASK_1GB = 0xC0000000, - IFC_AMASK_2GB = 0x80000000, - IFC_AMASK_4GB = 0x00000000, -}; - - -/* NOR Flash */ -#define FLASH_BASE 0xE8000000 - -#define FLASH_BANK_SIZE (128*1024*1024) -#define FLASH_PAGE_SIZE (1024) /* program buffer */ -#define FLASH_SECTOR_SIZE (128*1024) -#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE) -#define FLASH_CFI_16BIT 0x02 /* word */ -#define FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - - -#if 0 - #define ENABLE_CPLD -#endif -/* CPLD */ -#define CPLD_BASE 0xFFDF0000 -#define CPLD_BASE_PHYS_HIGH 0xFULL - -#define CPLD_SPARE 0x00 -#define CPLD_SATA_MUX_SEL 0x02 -#define CPLD_BANK_SEL 0x04 -#define CPLD_FW_REV 0x06 -#define CPLD_TTL_RW 0x08 -#define CPLD_TTL_LPBK 0x0A -#define CPLD_TTL_DATA 0x0C -#define CPLD_PROC_STATUS 0x0E /* write 1 to enable proc reset function, reset default value is 0 */ -#define CPLD_FPGA_RDY 0x10 /* read only when reg read 0x0DB1 then fpga is ready */ -#define CPLD_PCIE_SW_RESET 0x12 /* write 1 to reset the PCIe switch */ -#define CPLD_WR_TTL_INT_EN 0x14 -#define CPLD_WR_TTL_INT_DIR 0x16 -#define CPLD_INT_STAT 0x18 -#define CPLD_WR_TEMP_ALM_OVRD 0x1A /* write 0 to enable temp shutdown. reset default value is 1 */ -#define CPLD_PWR_DWN_CMD 0x1C -#define CPLD_TEMP_ALM_INT_STAT 0x1E -#define CPLD_WR_TEMP_ALM_INT_EN 0x20 - -#define CPLD_FLASH_BANK_0 0x00 -#define CPLD_FLASH_BANK_1 0x01 - -#define CPLD_DATA(n) *((volatile uint8_t*)(CPLD_BASE + n)) - - -/* SATA */ -#define SATA_ENBL (*(volatile uint32_t *)(0xB1003F4C)) /* also saw 0xB4003F4C */ - -/* DDR */ -/* NAII 68PPC2 - 8GB discrete DDR3 IM8G08D3EBDG-15E */ -/* 1333.333 MT/s data rate 8 GiB (DDR3, 64-bit, CL=9, ECC on) */ -#define DDR_N_RANKS 2 -#define DDR_RANK_DENS 0x100000000 -#define DDR_SDRAM_WIDTH 64 -#define DDR_EC_SDRAM_W 8 -#define DDR_N_ROW_ADDR 16 -#define DDR_N_COL_ADDR 10 -#define DDR_N_BANKS 8 -#define DDR_EDC_CONFIG 2 -#define DDR_BURSTL_MASK 0x0c -#define DDR_TCKMIN_X_PS 1500 -#define DDR_TCMMAX_PS 3000 -#define DDR_CASLAT_X 0x000007E0 -#define DDR_TAA_PS 13500 -#define DDR_TRCD_PS 13500 -#define DDR_TRP_PS 13500 -#define DDR_TRAS_PS 36000 -#define DDR_TRC_PS 49500 -#define DDR_TFAW_PS 30000 -#define DDR_TWR_PS 15000 -#define DDR_TRFC_PS 260000 -#define DDR_TRRD_PS 6000 -#define DDR_TWTR_PS 7500 -#define DDR_TRTP_PS 7500 -#define DDR_REF_RATE_PS 7800000 - -#define DDR_CS0_BNDS_VAL 0x000000FF -#define DDR_CS1_BNDS_VAL 0x010001FF -#define DDR_CS2_BNDS_VAL 0x0300033F -#define DDR_CS3_BNDS_VAL 0x0340037F -#define DDR_CS0_CONFIG_VAL 0x80044402 -#define DDR_CS1_CONFIG_VAL 0x80044402 -#define DDR_CS2_CONFIG_VAL 0x00000202 -#define DDR_CS3_CONFIG_VAL 0x00040202 -#define DDR_CS_CONFIG_2_VAL 0x00000000 - -#define DDR_TIMING_CFG_0_VAL 0xFF530004 -#define DDR_TIMING_CFG_1_VAL 0x98906345 -#define DDR_TIMING_CFG_2_VAL 0x0040A114 -#define DDR_TIMING_CFG_3_VAL 0x010A1100 -#define DDR_TIMING_CFG_4_VAL 0x00000001 -#define DDR_TIMING_CFG_5_VAL 0x04402400 - -#define DDR_SDRAM_MODE_VAL 0x00441C70 -#define DDR_SDRAM_MODE_2_VAL 0x00980000 -#define DDR_SDRAM_MODE_3_8_VAL 0x00000000 -#define DDR_SDRAM_MD_CNTL_VAL 0x00000000 - -#define DDR_SDRAM_CFG_VAL 0xE7040000 -#define DDR_SDRAM_CFG_2_VAL 0x00401010 - -#define DDR_SDRAM_INTERVAL_VAL 0x0C300100 -#define DDR_DATA_INIT_VAL 0xDEADBEEF -#define DDR_SDRAM_CLK_CNTL_VAL 0x02400000 -#define DDR_ZQ_CNTL_VAL 0x89080600 - -#define DDR_WRLVL_CNTL_VAL 0x8675F604 -#define DDR_WRLVL_CNTL_2_VAL 0x05060607 -#define DDR_WRLVL_CNTL_3_VAL 0x080A0A0B - -#define DDR_SDRAM_RCW_1_VAL 0x00000000 -#define DDR_SDRAM_RCW_2_VAL 0x00000000 - -#define DDR_DDRCDR_1_VAL 0x80040000 -#define DDR_DDRCDR_2_VAL 0x00000001 - -#define DDR_ERR_INT_EN_VAL 0x0000001D -#define DDR_ERR_SBE_VAL 0x00010000 - - -/* 12.4 DDR Memory Map */ -#define DDR_BASE (CCSRBAR + 0x8000) - -#define DDR_CS_BNDS(n) *((volatile uint32_t*)(DDR_BASE + 0x000 + (n * 8))) /* Chip select n memory bounds */ -#define DDR_CS_CONFIG(n) *((volatile uint32_t*)(DDR_BASE + 0x080 + (n * 4))) /* Chip select n configuration */ -#define DDR_CS_CONFIG_2(n) *((volatile uint32_t*)(DDR_BASE + 0x0C0 + (n * 4))) /* Chip select n configuration 2 */ -#define DDR_SDRAM_CFG *((volatile uint32_t*)(DDR_BASE + 0x110)) /* DDR SDRAM control configuration */ -#define DDR_SDRAM_CFG_2 *((volatile uint32_t*)(DDR_BASE + 0x114)) /* DDR SDRAM control configuration 2 */ -#define DDR_SDRAM_INTERVAL *((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */ -#define DDR_INIT_ADDR *((volatile uint32_t*)(DDR_BASE + 0x148)) /* DDR training initialization address */ -#define DDR_INIT_EXT_ADDR *((volatile uint32_t*)(DDR_BASE + 0x14C)) /* DDR training initialization extended address */ -#define DDR_DATA_INIT *((volatile uint32_t*)(DDR_BASE + 0x128)) /* DDR training initialization value */ -#define DDR_TIMING_CFG_0 *((volatile uint32_t*)(DDR_BASE + 0x104)) /* DDR SDRAM timing configuration 0 */ -#define DDR_TIMING_CFG_1 *((volatile uint32_t*)(DDR_BASE + 0x108)) /* DDR SDRAM timing configuration 1 */ -#define DDR_TIMING_CFG_2 *((volatile uint32_t*)(DDR_BASE + 0x10C)) /* DDR SDRAM timing configuration 2 */ -#define DDR_TIMING_CFG_3 *((volatile uint32_t*)(DDR_BASE + 0x100)) /* DDR SDRAM timing configuration 3 */ -#define DDR_TIMING_CFG_4 *((volatile uint32_t*)(DDR_BASE + 0x160)) /* DDR SDRAM timing configuration 4 */ -#define DDR_TIMING_CFG_5 *((volatile uint32_t*)(DDR_BASE + 0x164)) /* DDR SDRAM timing configuration 5 */ -#define DDR_TIMING_CFG_6 *((volatile uint32_t*)(DDR_BASE + 0x168)) /* DDR SDRAM timing configuration 6 */ -#define DDR_ZQ_CNTL *((volatile uint32_t*)(DDR_BASE + 0x170)) /* DDR ZQ calibration control */ -#define DDR_WRLVL_CNTL *((volatile uint32_t*)(DDR_BASE + 0x174)) /* DDR write leveling control */ -#define DDR_WRLVL_CNTL_2 *((volatile uint32_t*)(DDR_BASE + 0x190)) /* DDR write leveling control 2 */ -#define DDR_WRLVL_CNTL_3 *((volatile uint32_t*)(DDR_BASE + 0x194)) /* DDR write leveling control 3 */ -#define DDR_SR_CNTR *((volatile uint32_t*)(DDR_BASE + 0x17C)) /* DDR Self Refresh Counter */ -#define DDR_SDRAM_RCW_1 *((volatile uint32_t*)(DDR_BASE + 0x180)) /* DDR Register Control Word 1 */ -#define DDR_SDRAM_RCW_2 *((volatile uint32_t*)(DDR_BASE + 0x184)) /* DDR Register Control Word 2 */ -#define DDR_DDRCDR_1 *((volatile uint32_t*)(DDR_BASE + 0xB28)) /* DDR Control Driver Register 1 */ -#define DDR_DDRCDR_2 *((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */ -#define DDR_DDRDSR_1 *((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */ -#define DDR_DDRDSR_2 *((volatile uint32_t*)(DDR_BASE + 0xB24)) /* DDR Debug Status Register 2 */ -#define DDR_ERR_DISABLE *((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */ -#define DDR_ERR_INT_EN *((volatile uint32_t*)(DDR_BASE + 0xE48)) /* Memory error interrupt enable */ -#define DDR_ERR_SBE *((volatile uint32_t*)(DDR_BASE + 0xE58)) /* Single-Bit ECC memory error management */ -#define DDR_SDRAM_MODE *((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */ -#define DDR_SDRAM_MODE_2 *((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */ -#define DDR_SDRAM_MODE_3 *((volatile uint32_t*)(DDR_BASE + 0x200)) /* DDR SDRAM mode configuration 3 */ -#define DDR_SDRAM_MODE_4 *((volatile uint32_t*)(DDR_BASE + 0x204)) /* DDR SDRAM mode configuration 4 */ -#define DDR_SDRAM_MODE_5 *((volatile uint32_t*)(DDR_BASE + 0x208)) /* DDR SDRAM mode configuration 5 */ -#define DDR_SDRAM_MODE_6 *((volatile uint32_t*)(DDR_BASE + 0x20C)) /* DDR SDRAM mode configuration 6 */ -#define DDR_SDRAM_MODE_7 *((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */ -#define DDR_SDRAM_MODE_8 *((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */ -#define DDR_SDRAM_MD_CNTL *((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */ -#define DDR_SDRAM_CLK_CNTL *((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */ - -#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */ -#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */ - - -/* generic share NXP QorIQ driver code */ +/* generic shared NXP QorIQ driver code */ #include "nxp_ppc.c" @@ -307,20 +39,20 @@ void uart_init(void) */ uint32_t div = (((SYS_CLK / 2.0) / (16 * BAUD_RATE)) + 0.5); - while (!(UART_LSR(UART_SEL) & UART_LSR_TEMT)) + while (!(get8(UART_LSR(UART_SEL)) & UART_LSR_TEMT)) ; /* set ier, fcr, mcr */ - UART_IER(UART_SEL) = 0; - UART_FCR(UART_SEL) = (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN); + set8(UART_IER(UART_SEL), 0); + set8(UART_FCR(UART_SEL), (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN)); /* enable baud rate access (DLAB=1) - divisor latch access bit*/ - UART_LCR(UART_SEL) = (UART_LCR_DLAB | UART_LCR_WLS); + set8(UART_LCR(UART_SEL), (UART_LCR_DLAB | UART_LCR_WLS)); /* set divisor */ - UART_DLB(UART_SEL) = (div & 0xff); - UART_DMB(UART_SEL) = ((div>>8) & 0xff); + set8(UART_DLB(UART_SEL), (div & 0xff)); + set8(UART_DMB(UART_SEL), ((div>>8) & 0xff)); /* disable rate access (DLAB=0) */ - UART_LCR(UART_SEL) = (UART_LCR_WLS); + set8(UART_LCR(UART_SEL), (UART_LCR_WLS)); } void uart_write(const char* buf, uint32_t sz) @@ -329,11 +61,11 @@ void uart_write(const char* buf, uint32_t sz) while (sz-- > 0) { char c = buf[pos++]; if (c == '\n') { /* handle CRLF */ - while ((UART_LSR(UART_SEL) & UART_LSR_THRE) == 0); - UART_THR(UART_SEL) = '\r'; + while ((get8(UART_LSR(UART_SEL)) & UART_LSR_THRE) == 0); + set8(UART_THR(UART_SEL), '\r'); } - while ((UART_LSR(UART_SEL) & UART_LSR_THRE) == 0); - UART_THR(UART_SEL) = c; + while ((get8(UART_LSR(UART_SEL)) & UART_LSR_THRE) == 0); + set8(UART_THR(UART_SEL), c); } } #endif /* DEBUG_UART */ @@ -344,6 +76,13 @@ void law_init(void) set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB, 1); } +/* Delay helper using timebase */ +#define DELAY_US (SYS_CLK / 1000000) +static void udelay(uint32_t delay_us) +{ + wait_ticks(delay_us * DELAY_US); +} + static void hal_flash_init(void) { /* IFC - NOR Flash */ @@ -351,107 +90,138 @@ static void hal_flash_init(void) set_law(1, FLASH_BASE_PHYS_HIGH, FLASH_BASE, LAW_TRGT_IFC, LAW_SIZE_128MB, 1); /* NOR IFC Flash Timing Parameters */ - IFC_FTIM0(0) = (IFC_FTIM0_NOR_TACSE(4) | \ - IFC_FTIM0_NOR_TEADC(5) | \ - IFC_FTIM0_NOR_TEAHC(5)); - IFC_FTIM1(0) = (IFC_FTIM1_NOR_TACO(53) | - IFC_FTIM1_NOR_TRAD(26) | - IFC_FTIM1_NOR_TSEQ(19)); - IFC_FTIM2(0) = (IFC_FTIM2_NOR_TCS(4) | - IFC_FTIM2_NOR_TCH(4) | - IFC_FTIM2_NOR_TWPH(14) | - IFC_FTIM2_NOR_TWP(28)); - IFC_FTIM3(0) = 0; + set32(IFC_FTIM0(0), (IFC_FTIM0_NOR_TACSE(4) | + IFC_FTIM0_NOR_TEADC(5) | + IFC_FTIM0_NOR_TEAHC(5))); + set32(IFC_FTIM1(0), (IFC_FTIM1_NOR_TACO(53) | + IFC_FTIM1_NOR_TRAD(26) | + IFC_FTIM1_NOR_TSEQ(19))); + set32(IFC_FTIM2(0), (IFC_FTIM2_NOR_TCS(4) | + IFC_FTIM2_NOR_TCH(4) | + IFC_FTIM2_NOR_TWPH(14) | + IFC_FTIM2_NOR_TWP(28))); + set32(IFC_FTIM3(0), 0); /* NOR IFC Definitions (CS0) */ - IFC_CSPR_EXT(0) = (0xF); - IFC_CSPR(0) = (IFC_CSPR_PHYS_ADDR(FLASH_BASE) | \ - IFC_CSPR_PORT_SIZE_16 | \ - IFC_CSPR_MSEL_NOR | \ - IFC_CSPR_V); - IFC_AMASK(0) = IFC_AMASK_128MB; - IFC_CSOR(0) = 0x0000000C; /* TRHZ (80 clocks for read enable high) */ + set32(IFC_CSPR_EXT(0), 0xF); + set32(IFC_CSPR(0), (IFC_CSPR_PHYS_ADDR(FLASH_BASE) | + IFC_CSPR_PORT_SIZE_16 | + IFC_CSPR_MSEL_NOR | + IFC_CSPR_V)); + set32(IFC_AMASK(0), IFC_AMASK_128MB); + set32(IFC_CSOR(0), 0x0000000C); /* TRHZ (80 clocks for read enable high) */ } static void hal_ddr_init(void) { #ifdef ENABLE_DDR + uint32_t reg; + /* Map LAW for DDR */ - set_law(4, 0, 0, LAW_TRGT_DDR_1, LAW_SIZE_2GB, 0); + set_law(4, 0, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB, 0); /* If DDR is already enabled then just return */ - if (DDR_SDRAM_CFG & DDR_SDRAM_CFG_MEM_EN) { + if (get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN) { return; } + /* Set clock early for clock / pin */ + set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL); + /* Setup DDR CS (chip select) bounds */ - DDR_CS_BNDS(0) = DDR_CS0_BNDS_VAL; - DDR_CS_CONFIG(0) = DDR_CS0_CONFIG_VAL; - DDR_CS_CONFIG_2(0) = DDR_CS_CONFIG_2_VAL; - DDR_CS_BNDS(1) = DDR_CS1_BNDS_VAL; - DDR_CS_CONFIG(1) = DDR_CS1_CONFIG_VAL; - DDR_CS_CONFIG_2(1) = DDR_CS_CONFIG_2_VAL; - DDR_CS_BNDS(2) = DDR_CS2_BNDS_VAL; - DDR_CS_CONFIG(2) = DDR_CS2_CONFIG_VAL; - DDR_CS_CONFIG_2(2) = DDR_CS_CONFIG_2_VAL; - DDR_CS_BNDS(3) = DDR_CS3_BNDS_VAL; - DDR_CS_CONFIG(3) = DDR_CS3_CONFIG_VAL; - DDR_CS_CONFIG_2(3) = DDR_CS_CONFIG_2_VAL; + set32(DDR_CS_BNDS(0), DDR_CS0_BNDS_VAL); + set32(DDR_CS_CONFIG(0), DDR_CS0_CONFIG_VAL); + set32(DDR_CS_CONFIG_2(0), DDR_CS_CONFIG_2_VAL); + set32(DDR_CS_BNDS(1), DDR_CS1_BNDS_VAL); + set32(DDR_CS_CONFIG(1), DDR_CS1_CONFIG_VAL); + set32(DDR_CS_CONFIG_2(1), DDR_CS_CONFIG_2_VAL); + set32(DDR_CS_BNDS(2), DDR_CS2_BNDS_VAL); + set32(DDR_CS_CONFIG(2), DDR_CS2_CONFIG_VAL); + set32(DDR_CS_CONFIG_2(2), DDR_CS_CONFIG_2_VAL); + set32(DDR_CS_BNDS(3), DDR_CS3_BNDS_VAL); + set32(DDR_CS_CONFIG(3), DDR_CS3_CONFIG_VAL); + set32(DDR_CS_CONFIG_2(3), DDR_CS_CONFIG_2_VAL); /* DDR SDRAM timing configuration */ - DDR_TIMING_CFG_0 = DDR_TIMING_CFG_0_VAL; - DDR_TIMING_CFG_1 = DDR_TIMING_CFG_1_VAL; - DDR_TIMING_CFG_2 = DDR_TIMING_CFG_2_VAL; - DDR_TIMING_CFG_3 = DDR_TIMING_CFG_3_VAL; - DDR_TIMING_CFG_4 = DDR_TIMING_CFG_4_VAL; - DDR_TIMING_CFG_5 = DDR_TIMING_CFG_5_VAL; + set32(DDR_TIMING_CFG_3, DDR_TIMING_CFG_3_VAL); + set32(DDR_TIMING_CFG_0, DDR_TIMING_CFG_0_VAL); + set32(DDR_TIMING_CFG_1, DDR_TIMING_CFG_1_VAL); + set32(DDR_TIMING_CFG_2, DDR_TIMING_CFG_2_VAL); + set32(DDR_TIMING_CFG_4, DDR_TIMING_CFG_4_VAL); + set32(DDR_TIMING_CFG_5, DDR_TIMING_CFG_5_VAL); + + set32(DDR_ZQ_CNTL, DDR_ZQ_CNTL_VAL); /* DDR SDRAM mode configuration */ - DDR_SDRAM_MODE = DDR_SDRAM_MODE_VAL; - DDR_SDRAM_MODE_2 = DDR_SDRAM_MODE_2_VAL; - DDR_SDRAM_MODE_3 = DDR_SDRAM_MODE_3_8_VAL; - DDR_SDRAM_MODE_4 = DDR_SDRAM_MODE_3_8_VAL; - DDR_SDRAM_MODE_5 = DDR_SDRAM_MODE_3_8_VAL; - DDR_SDRAM_MODE_6 = DDR_SDRAM_MODE_3_8_VAL; - DDR_SDRAM_MODE_7 = DDR_SDRAM_MODE_3_8_VAL; - DDR_SDRAM_MODE_8 = DDR_SDRAM_MODE_3_8_VAL; - DDR_SDRAM_MD_CNTL = DDR_SDRAM_MD_CNTL_VAL; + set32(DDR_SDRAM_MODE, DDR_SDRAM_MODE_VAL); + set32(DDR_SDRAM_MODE_2, DDR_SDRAM_MODE_2_VAL); + set32(DDR_SDRAM_MODE_3, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MODE_4, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MODE_5, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MODE_6, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MODE_7, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MODE_8, DDR_SDRAM_MODE_3_8_VAL); + set32(DDR_SDRAM_MD_CNTL, DDR_SDRAM_MD_CNTL_VAL); /* DDR Configuration */ - DDR_SDRAM_INTERVAL = DDR_SDRAM_INTERVAL_VAL; - DDR_SDRAM_CLK_CNTL = DDR_SDRAM_CLK_CNTL_VAL; - DDR_DATA_INIT = DDR_DATA_INIT_VAL; - DDR_ZQ_CNTL = DDR_ZQ_CNTL_VAL; - DDR_WRLVL_CNTL = DDR_WRLVL_CNTL_VAL; - DDR_WRLVL_CNTL_2 = DDR_WRLVL_CNTL_2_VAL; - DDR_WRLVL_CNTL_3 = DDR_WRLVL_CNTL_3_VAL; - DDR_SR_CNTR = 0; - DDR_SDRAM_RCW_1 = 0; - DDR_SDRAM_RCW_2 = 0; - DDR_DDRCDR_1 = DDR_DDRCDR_1_VAL; - DDR_DDRCDR_2 = DDR_DDRCDR_2_VAL; - DDR_SDRAM_CFG_2 = DDR_SDRAM_CFG_2_VAL; - DDR_INIT_ADDR = 0; - DDR_INIT_EXT_ADDR = 0; - DDR_ERR_DISABLE = 0; - DDR_ERR_INT_EN = DDR_ERR_INT_EN_VAL; - DDR_ERR_SBE = DDR_ERR_SBE_VAL; + set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL); + set32(DDR_DATA_INIT, DDR_DATA_INIT_VAL); + set32(DDR_WRLVL_CNTL, DDR_WRLVL_CNTL_VAL); + set32(DDR_WRLVL_CNTL_2, DDR_WRLVL_CNTL_2_VAL); + set32(DDR_WRLVL_CNTL_3, DDR_WRLVL_CNTL_3_VAL); + set32(DDR_SR_CNTR, 0); + set32(DDR_SDRAM_RCW_1, 0); + set32(DDR_SDRAM_RCW_2, 0); + set32(DDR_DDRCDR_1, DDR_DDRCDR_1_VAL); + set32(DDR_SDRAM_CFG_2, (DDR_SDRAM_CFG_2_VAL | DDR_SDRAM_CFG_2_D_INIT)); + set32(DDR_INIT_ADDR, 0); + set32(DDR_INIT_EXT_ADDR, 0); + set32(DDR_DDRCDR_2, DDR_DDRCDR_2_VAL); + set32(DDR_ERR_DISABLE, 0); + set32(DDR_ERR_INT_EN, DDR_ERR_INT_EN_VAL); + set32(DDR_ERR_SBE, DDR_ERR_SBE_VAL); /* Set values, but do not enable the DDR yet */ - DDR_SDRAM_CFG = (DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN); + set32(DDR_SDRAM_CFG, DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN); + __asm__ __volatile__("sync;isync"); - /* TODO: Errata A009942 */ + /* busy wait for ~500us */ + udelay(500); + __asm__ __volatile__("sync;isync"); /* Enable controller */ - DDR_SDRAM_CFG |= DDR_SDRAM_CFG_MEM_EN; + reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI; + set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN); __asm__ __volatile__("sync;isync"); - /* Wait for data initialization is complete */ - while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG_2_D_INIT)); -#endif + /* Wait for data initialization to complete */ + while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) { + /* busy wait loop - throttle polling */ + udelay(10000); + } +#endif /* ENABLE_DDR */ } void hal_early_init(void) { + /* Enable timebase on core 0 */ + set32(RCPM_PCTBENR, (1 << 0)); + + /* Only invalidate the CPC if it is NOT configured as SRAM. + * When CPC SRAM is active (used as stack), writing CPCFI|CPCLFC + * without preserving CPCE would disable the CPC and corrupt the + * stack. Skip invalidation when SRAMEN is set (T2080RM 8.4.2.2). */ + if (!(get32((volatile uint32_t*)(CPC_BASE + CPCSRCR0)) & CPCSRCR0_SRAMEN)) { + set32((volatile uint32_t*)(CPC_BASE + CPCCSR0), + (CPCCSR0_CPCFI | CPCCSR0_CPCLFC)); + /* Wait for self-clearing invalidate bits */ + while (get32((volatile uint32_t*)(CPC_BASE + CPCCSR0)) & + (CPCCSR0_CPCFI | CPCCSR0_CPCLFC)); + } + + /* Set DCSR space = 1G */ + set32(DCFG_DCSR, (get32(DCFG_DCSR) | CORENET_DCSR_SZ_1G)); + get32(DCFG_DCSR); /* read back to sync */ + hal_ddr_init(); } @@ -459,24 +229,24 @@ static void hal_cpld_init(void) { #ifdef ENABLE_CPLD /* CPLD IFC Timing Parameters */ - IFC_FTIM0(3) = (IFC_FTIM0_GPCM_TACSE(16UL) | - IFC_FTIM0_GPCM_TEADC(16UL) | - IFC_FTIM0_GPCM_TEAHC(16UL)); - IFC_FTIM1(3) = (IFC_FTIM1_GPCM_TACO(16UL) | - IFC_FTIM1_GPCM_TRAD(31UL)); - IFC_FTIM2(3) = (IFC_FTIM2_GPCM_TCS(16UL) | - IFC_FTIM2_GPCM_TCH(8UL) | - IFC_FTIM2_GPCM_TWP(31UL)); - IFC_FTIM3(3) = 0; + set32(IFC_FTIM0(3), (IFC_FTIM0_GPCM_TACSE(16UL) | + IFC_FTIM0_GPCM_TEADC(16UL) | + IFC_FTIM0_GPCM_TEAHC(16UL))); + set32(IFC_FTIM1(3), (IFC_FTIM1_GPCM_TACO(16UL) | + IFC_FTIM1_GPCM_TRAD(31UL))); + set32(IFC_FTIM2(3), (IFC_FTIM2_GPCM_TCS(16UL) | + IFC_FTIM2_GPCM_TCH(8UL) | + IFC_FTIM2_GPCM_TWP(31UL))); + set32(IFC_FTIM3(3), 0); /* CPLD IFC Definitions (CS3) */ - IFC_CSPR_EXT(3) = CPLD_BASE_PHYS_HIGH; - IFC_CSPR(3) = (IFC_CSPR_PHYS_ADDR(CPLD_BASE) | - IFC_CSPR_PORT_SIZE_16 | - IFC_CSPR_MSEL_GPCM | - IFC_CSPR_V); - IFC_AMASK(3) = IFC_AMASK_64KB; - IFC_CSOR(3) = 0; + set32(IFC_CSPR_EXT(3), CPLD_BASE_PHYS_HIGH); + set32(IFC_CSPR(3), (IFC_CSPR_PHYS_ADDR(CPLD_BASE) | + IFC_CSPR_PORT_SIZE_16 | + IFC_CSPR_MSEL_GPCM | + IFC_CSPR_V)); + set32(IFC_AMASK(3), IFC_AMASK_64KB); + set32(IFC_CSOR(3), 0); /* IFC - CPLD */ set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, @@ -495,6 +265,9 @@ void hal_init(void) uint32_t fw; #endif + /* Enable timebase on core 0 */ + set32(RCPM_PCTBENR, (1 << 0)); + law_init(); #ifdef DEBUG_UART @@ -506,19 +279,14 @@ void hal_init(void) hal_cpld_init(); #ifdef ENABLE_CPLD - CPLD_DATA(CPLD_PROC_STATUS) = 1; /* Enable proc reset */ - CPLD_DATA(CPLD_WR_TEMP_ALM_OVRD) = 0; /* Enable temp alarm */ + set8(CPLD_DATA(CPLD_PROC_STATUS), 1); /* Enable proc reset */ + set8(CPLD_DATA(CPLD_WR_TEMP_ALM_OVRD), 0); /* Enable temp alarm */ #ifdef DEBUG_UART - fw = CPLD_DATA(CPLD_FW_REV); + fw = get8(CPLD_DATA(CPLD_FW_REV)); wolfBoot_printf("CPLD FW Rev: 0x%x\n", fw); #endif #endif /* ENABLE_CPLD */ - -#if 0 /* not tested */ - /* Disable SATA Write Protection */ - SATA_ENBL = 0; -#endif } int hal_flash_write(uint32_t address, const uint8_t *data, int len) diff --git a/hal/nxp_t2080.h b/hal/nxp_t2080.h new file mode 100644 index 0000000000..7f5b492b12 --- /dev/null +++ b/hal/nxp_t2080.h @@ -0,0 +1,312 @@ +/* nxp_t2080.h + * + * Copyright (C) 2025 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + * + * Board: NAII 68PPC2 + * NXP T2080E Rev 1.1, e6500 core 2.0, PVR 8040_0120 and SVR 8538_0011 + */ + +#ifndef NXP_T2080_H +#define NXP_T2080_H + +#include "nxp_ppc.h" + +/* T2080 System Clock */ +#define SYS_CLK (600000000) /* 100MHz PLL with 6:1 = 600 MHz */ + +/* ---- UART (PC16552D Dual UART) ---- */ +#define BAUD_RATE 115200 +#define UART_SEL 0 /* select UART 0 or 1 */ + +#define UART_BASE(n) (CCSRBAR + 0x11C500 + (n * 0x1000)) + +#define UART_RBR(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* receiver buffer register */ +#define UART_THR(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* transmitter holding register */ +#define UART_IER(n) ((volatile uint8_t*)(UART_BASE(n) + 1)) /* interrupt enable register */ +#define UART_IIR(n) ((volatile uint8_t*)(UART_BASE(n) + 2)) /* interrupt ID register */ +#define UART_FCR(n) ((volatile uint8_t*)(UART_BASE(n) + 2)) /* FIFO control register */ +#define UART_LCR(n) ((volatile uint8_t*)(UART_BASE(n) + 3)) /* line control register */ +#define UART_MCR(n) ((volatile uint8_t*)(UART_BASE(n) + 4)) /* modem control register */ +#define UART_LSR(n) ((volatile uint8_t*)(UART_BASE(n) + 5)) /* line status register */ + +/* enabled when UART_LCR_DLAB set */ +#define UART_DLB(n) ((volatile uint8_t*)(UART_BASE(n) + 0)) /* divisor least significant byte register */ +#define UART_DMB(n) ((volatile uint8_t*)(UART_BASE(n) + 1)) /* divisor most significant byte register */ + +#define UART_FCR_TFR (0x04) /* Transmitter FIFO reset */ +#define UART_FCR_RFR (0x02) /* Receiver FIFO reset */ +#define UART_FCR_FEN (0x01) /* FIFO enable */ +#define UART_LCR_DLAB (0x80) /* Divisor latch access bit */ +#define UART_LCR_WLS (0x03) /* Word length select: 8-bits */ +#define UART_LSR_TEMT (0x40) /* Transmitter empty */ +#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */ + + +/* ---- IFC (Integrated Flash Controller) - T2080RM 13.3 ---- */ +#define IFC_BASE (CCSRBAR + 0x00124000) +#define IFC_MAX_BANKS 8 + +#define IFC_CSPR_EXT(n) ((volatile uint32_t*)(IFC_BASE + 0x000C + (n * 0xC))) /* Extended Base Address */ +#define IFC_CSPR(n) ((volatile uint32_t*)(IFC_BASE + 0x0010 + (n * 0xC))) /* Chip-select Property */ +#define IFC_AMASK(n) ((volatile uint32_t*)(IFC_BASE + 0x00A0 + (n * 0xC))) +#define IFC_CSOR(n) ((volatile uint32_t*)(IFC_BASE + 0x0130 + (n * 0xC))) +#define IFC_CSOR_EXT(n) ((volatile uint32_t*)(IFC_BASE + 0x0134 + (n * 0xC))) +#define IFC_FTIM0(n) ((volatile uint32_t*)(IFC_BASE + 0x01C0 + (n * 0x30))) +#define IFC_FTIM1(n) ((volatile uint32_t*)(IFC_BASE + 0x01C4 + (n * 0x30))) +#define IFC_FTIM2(n) ((volatile uint32_t*)(IFC_BASE + 0x01C8 + (n * 0x30))) +#define IFC_FTIM3(n) ((volatile uint32_t*)(IFC_BASE + 0x01CC + (n * 0x30))) + +#define IFC_CSPR_PHYS_ADDR(x) (((uint32_t)x) & 0xFFFF0000) /* Physical base address */ +#define IFC_CSPR_PORT_SIZE_8 0x00000080 /* Port Size 8 */ +#define IFC_CSPR_PORT_SIZE_16 0x00000100 /* Port Size 16 */ +#define IFC_CSPR_WP 0x00000040 /* Write Protect */ +#define IFC_CSPR_MSEL_NOR 0x00000000 /* Mode Select - NOR */ +#define IFC_CSPR_MSEL_NAND 0x00000002 /* Mode Select - NAND */ +#define IFC_CSPR_MSEL_GPCM 0x00000004 /* Mode Select - GPCM (General-purpose chip-select machine) */ +#define IFC_CSPR_V 0x00000001 /* Bank Valid */ + +/* NOR Timings (IFC clocks) */ +#define IFC_FTIM0_NOR_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */ +#define IFC_FTIM0_NOR_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */ +#define IFC_FTIM0_NOR_TAVDS(n) (((n) & 0x3F) << 8) /* Delay between CS assertion */ +#define IFC_FTIM0_NOR_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */ +#define IFC_FTIM1_NOR_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */ +#define IFC_FTIM1_NOR_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */ +#define IFC_FTIM1_NOR_TSEQ(n) (((n) & 0x3F) << 0) /* sequential read access delay */ +#define IFC_FTIM2_NOR_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */ +#define IFC_FTIM2_NOR_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */ +#define IFC_FTIM2_NOR_TWPH(n) (((n) & 0x3F) << 10) /* Chip-select hold time */ +#define IFC_FTIM2_NOR_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */ + +/* GPCM Timings (IFC clocks) */ +#define IFC_FTIM0_GPCM_TACSE(n) (((n) & 0x0F) << 28) /* After address hold cycle */ +#define IFC_FTIM0_GPCM_TEADC(n) (((n) & 0x3F) << 16) /* External latch address delay cycles */ +#define IFC_FTIM0_GPCM_TEAHC(n) (((n) & 0x3F) << 0) /* External latch address hold cycles */ +#define IFC_FTIM1_GPCM_TACO(n) (((n) & 0xFF) << 24) /* CS assertion to output enable */ +#define IFC_FTIM1_GPCM_TRAD(n) (((n) & 0x3F) << 8) /* read access delay */ +#define IFC_FTIM2_GPCM_TCS(n) (((n) & 0x0F) << 24) /* Chip-select assertion setup time */ +#define IFC_FTIM2_GPCM_TCH(n) (((n) & 0x0F) << 18) /* Chip-select hold time */ +#define IFC_FTIM2_GPCM_TWP(n) (((n) & 0xFF) << 0) /* Write enable pulse width */ + +/* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */ +enum ifc_amask_sizes { + IFC_AMASK_64KB = 0xFFFF0000, + IFC_AMASK_128KB = 0xFFFE0000, + IFC_AMASK_256KB = 0xFFFC0000, + IFC_AMASK_512KB = 0xFFF80000, + IFC_AMASK_1MB = 0xFFF00000, + IFC_AMASK_2MB = 0xFFE00000, + IFC_AMASK_4MB = 0xFFC00000, + IFC_AMASK_8MB = 0xFF800000, + IFC_AMASK_16MB = 0xFF000000, + IFC_AMASK_32MB = 0xFE000000, + IFC_AMASK_64MB = 0xFC000000, + IFC_AMASK_128MB = 0xF8000000, + IFC_AMASK_256MB = 0xF0000000, + IFC_AMASK_512MB = 0xE0000000, + IFC_AMASK_1GB = 0xC0000000, + IFC_AMASK_2GB = 0x80000000, + IFC_AMASK_4GB = 0x00000000, +}; + + +/* ---- NOR Flash ---- */ +#define FLASH_BASE 0xE8000000 + +#define FLASH_BANK_SIZE (128*1024*1024) +#define FLASH_PAGE_SIZE (1024) /* program buffer */ +#define FLASH_SECTOR_SIZE (128*1024) +#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE) +#define FLASH_CFI_16BIT 0x02 /* word */ +#define FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + + +/* ---- CPLD ---- */ +#if 0 + #define ENABLE_CPLD +#endif +#define CPLD_BASE 0xFFDF0000 +#define CPLD_BASE_PHYS_HIGH 0xFULL + +#define CPLD_SPARE 0x00 +#define CPLD_SATA_MUX_SEL 0x02 +#define CPLD_BANK_SEL 0x04 +#define CPLD_FW_REV 0x06 +#define CPLD_TTL_RW 0x08 +#define CPLD_TTL_LPBK 0x0A +#define CPLD_TTL_DATA 0x0C +#define CPLD_PROC_STATUS 0x0E /* write 1 to enable proc reset function, reset default value is 0 */ +#define CPLD_FPGA_RDY 0x10 /* read only when reg read 0x0DB1 then fpga is ready */ +#define CPLD_PCIE_SW_RESET 0x12 /* write 1 to reset the PCIe switch */ +#define CPLD_WR_TTL_INT_EN 0x14 +#define CPLD_WR_TTL_INT_DIR 0x16 +#define CPLD_INT_STAT 0x18 +#define CPLD_WR_TEMP_ALM_OVRD 0x1A /* write 0 to enable temp shutdown. reset default value is 1 */ +#define CPLD_PWR_DWN_CMD 0x1C +#define CPLD_TEMP_ALM_INT_STAT 0x1E +#define CPLD_WR_TEMP_ALM_INT_EN 0x20 + +#define CPLD_FLASH_BANK_0 0x00 +#define CPLD_FLASH_BANK_1 0x01 + +#define CPLD_DATA(n) ((volatile uint8_t*)(CPLD_BASE + n)) + + +/* ---- SATA ---- */ +#define SATA_ENBL ((volatile uint32_t*)0xB1003F4C) /* also saw 0xB4003F4C */ + + +/* ---- DCFG (Device Configuration) - T2080RM 6.3 ---- */ +#define DCFG_BASE (CCSRBAR + 0xE0000) +#define DCFG_DCSR ((volatile uint32_t*)(DCFG_BASE + 0x704)) /* Debug Configuration and Status */ +#define DCFG_DEVDISR1 ((volatile uint32_t*)(DCFG_BASE + 0x070)) /* Device Disable Control 1 */ +#define DCFG_DEVDISR2 ((volatile uint32_t*)(DCFG_BASE + 0x074)) /* Device Disable Control 2 */ +#define DCFG_DEVDISR3 ((volatile uint32_t*)(DCFG_BASE + 0x078)) /* Device Disable Control 3 */ +#define DCFG_DEVDISR4 ((volatile uint32_t*)(DCFG_BASE + 0x07C)) /* Device Disable Control 4 */ +#define DCFG_DEVDISR5 ((volatile uint32_t*)(DCFG_BASE + 0x080)) /* Device Disable Control 5 */ + +/* ---- RCPM (Run Control and Power Management) - T2080RM 6.4 ---- */ +#define RCPM_BASE (CCSRBAR + 0xE2000) +#define RCPM_PCTBENR ((volatile uint32_t*)(RCPM_BASE + 0x1A0)) /* Physical Core Timebase Enable */ + + +/* ---- DDR (T2080RM 12.4) ---- */ +/* NAII 68PPC2 - 8GB discrete DDR3 IM8G08D3EBDG-15E */ +/* 1333.333 MT/s data rate 8 GiB (DDR3, 64-bit, CL=9, ECC on) */ +#define DDR_N_RANKS 2 +#define DDR_RANK_DENS 0x100000000 +#define DDR_SDRAM_WIDTH 64 +#define DDR_EC_SDRAM_W 8 +#define DDR_N_ROW_ADDR 16 +#define DDR_N_COL_ADDR 10 +#define DDR_N_BANKS 8 +#define DDR_EDC_CONFIG 2 +#define DDR_BURSTL_MASK 0x0c +#define DDR_TCKMIN_X_PS 1500 +#define DDR_TCMMAX_PS 3000 +#define DDR_CASLAT_X 0x000007E0 +#define DDR_TAA_PS 13500 +#define DDR_TRCD_PS 13500 +#define DDR_TRP_PS 13500 +#define DDR_TRAS_PS 36000 +#define DDR_TRC_PS 49500 +#define DDR_TFAW_PS 30000 +#define DDR_TWR_PS 15000 +#define DDR_TRFC_PS 260000 +#define DDR_TRRD_PS 6000 +#define DDR_TWTR_PS 7500 +#define DDR_TRTP_PS 7500 +#define DDR_REF_RATE_PS 7800000 + +#define DDR_CS0_BNDS_VAL 0x000000FF +#define DDR_CS1_BNDS_VAL 0x010001FF +#define DDR_CS2_BNDS_VAL 0x0300033F +#define DDR_CS3_BNDS_VAL 0x0340037F +#define DDR_CS0_CONFIG_VAL 0x80044402 +#define DDR_CS1_CONFIG_VAL 0x80044402 +#define DDR_CS2_CONFIG_VAL 0x00000202 +#define DDR_CS3_CONFIG_VAL 0x00040202 +#define DDR_CS_CONFIG_2_VAL 0x00000000 + +#define DDR_TIMING_CFG_0_VAL 0xFF550004 +#define DDR_TIMING_CFG_1_VAL 0xBCB48C56 +#define DDR_TIMING_CFG_2_VAL 0x0040C114 +#define DDR_TIMING_CFG_3_VAL 0x010C1000 +#define DDR_TIMING_CFG_4_VAL 0x00000001 +#define DDR_TIMING_CFG_5_VAL 0x03402400 + +#define DDR_SDRAM_MODE_VAL 0x00441C70 +#define DDR_SDRAM_MODE_2_VAL 0x00980000 +#define DDR_SDRAM_MODE_3_8_VAL 0x00000000 +#define DDR_SDRAM_MD_CNTL_VAL 0x00000000 + +#define DDR_SDRAM_CFG_VAL 0xE7044000 +#define DDR_SDRAM_CFG_2_VAL 0x00401050 + +#define DDR_SDRAM_INTERVAL_VAL 0x0C300100 +#define DDR_DATA_INIT_VAL 0xDEADBEEF +#define DDR_SDRAM_CLK_CNTL_VAL 0x02400000 +#define DDR_ZQ_CNTL_VAL 0x89080600 + +#define DDR_WRLVL_CNTL_VAL 0x8675F608 +#define DDR_WRLVL_CNTL_2_VAL 0x080A0A0C +#define DDR_WRLVL_CNTL_3_VAL 0x0C0E0E0D + +#define DDR_SDRAM_RCW_1_VAL 0x00000000 +#define DDR_SDRAM_RCW_2_VAL 0x00000000 + +#define DDR_DDRCDR_1_VAL 0x80040000 +#define DDR_DDRCDR_2_VAL 0x00000001 + +#define DDR_ERR_INT_EN_VAL 0x0000001D +#define DDR_ERR_SBE_VAL 0x00010000 + + +/* 12.4 DDR Memory Map */ +#define DDR_BASE (CCSRBAR + 0x8000) + +#define DDR_CS_BNDS(n) ((volatile uint32_t*)(DDR_BASE + 0x000 + (n * 8))) /* Chip select n memory bounds */ +#define DDR_CS_CONFIG(n) ((volatile uint32_t*)(DDR_BASE + 0x080 + (n * 4))) /* Chip select n configuration */ +#define DDR_CS_CONFIG_2(n) ((volatile uint32_t*)(DDR_BASE + 0x0C0 + (n * 4))) /* Chip select n configuration 2 */ +#define DDR_TIMING_CFG_3 ((volatile uint32_t*)(DDR_BASE + 0x100)) /* DDR SDRAM timing configuration 3 */ +#define DDR_TIMING_CFG_0 ((volatile uint32_t*)(DDR_BASE + 0x104)) /* DDR SDRAM timing configuration 0 */ +#define DDR_TIMING_CFG_1 ((volatile uint32_t*)(DDR_BASE + 0x108)) /* DDR SDRAM timing configuration 1 */ +#define DDR_TIMING_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x10C)) /* DDR SDRAM timing configuration 2 */ +#define DDR_SDRAM_CFG ((volatile uint32_t*)(DDR_BASE + 0x110)) /* DDR SDRAM control configuration */ +#define DDR_SDRAM_CFG_2 ((volatile uint32_t*)(DDR_BASE + 0x114)) /* DDR SDRAM control configuration 2 */ +#define DDR_SDRAM_MODE ((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */ +#define DDR_SDRAM_MODE_2 ((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */ +#define DDR_SDRAM_MD_CNTL ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */ +#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */ +#define DDR_DATA_INIT ((volatile uint32_t*)(DDR_BASE + 0x128)) /* DDR training initialization value */ +#define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */ +#define DDR_INIT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x148)) /* DDR training initialization address */ +#define DDR_INIT_EXT_ADDR ((volatile uint32_t*)(DDR_BASE + 0x14C)) /* DDR training initialization extended address */ +#define DDR_TIMING_CFG_4 ((volatile uint32_t*)(DDR_BASE + 0x160)) /* DDR SDRAM timing configuration 4 */ +#define DDR_TIMING_CFG_5 ((volatile uint32_t*)(DDR_BASE + 0x164)) /* DDR SDRAM timing configuration 5 */ +#define DDR_TIMING_CFG_6 ((volatile uint32_t*)(DDR_BASE + 0x168)) /* DDR SDRAM timing configuration 6 */ +#define DDR_ZQ_CNTL ((volatile uint32_t*)(DDR_BASE + 0x170)) /* DDR ZQ calibration control */ +#define DDR_WRLVL_CNTL ((volatile uint32_t*)(DDR_BASE + 0x174)) /* DDR write leveling control */ +#define DDR_SR_CNTR ((volatile uint32_t*)(DDR_BASE + 0x17C)) /* DDR Self Refresh Counter */ +#define DDR_SDRAM_RCW_1 ((volatile uint32_t*)(DDR_BASE + 0x180)) /* DDR Register Control Word 1 */ +#define DDR_SDRAM_RCW_2 ((volatile uint32_t*)(DDR_BASE + 0x184)) /* DDR Register Control Word 2 */ +#define DDR_WRLVL_CNTL_2 ((volatile uint32_t*)(DDR_BASE + 0x190)) /* DDR write leveling control 2 */ +#define DDR_WRLVL_CNTL_3 ((volatile uint32_t*)(DDR_BASE + 0x194)) /* DDR write leveling control 3 */ +#define DDR_SDRAM_MODE_3 ((volatile uint32_t*)(DDR_BASE + 0x200)) /* DDR SDRAM mode configuration 3 */ +#define DDR_SDRAM_MODE_4 ((volatile uint32_t*)(DDR_BASE + 0x204)) /* DDR SDRAM mode configuration 4 */ +#define DDR_SDRAM_MODE_5 ((volatile uint32_t*)(DDR_BASE + 0x208)) /* DDR SDRAM mode configuration 5 */ +#define DDR_SDRAM_MODE_6 ((volatile uint32_t*)(DDR_BASE + 0x20C)) /* DDR SDRAM mode configuration 6 */ +#define DDR_SDRAM_MODE_7 ((volatile uint32_t*)(DDR_BASE + 0x210)) /* DDR SDRAM mode configuration 7 */ +#define DDR_SDRAM_MODE_8 ((volatile uint32_t*)(DDR_BASE + 0x214)) /* DDR SDRAM mode configuration 8 */ +#define DDR_DDRCDR_1 ((volatile uint32_t*)(DDR_BASE + 0xB28)) /* DDR Control Driver Register 1 */ +#define DDR_DDRCDR_2 ((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */ +#define DDR_DDRDSR_1 ((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */ +#define DDR_DDRDSR_2 ((volatile uint32_t*)(DDR_BASE + 0xB24)) /* DDR Debug Status Register 2 */ +#define DDR_ERR_DISABLE ((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */ +#define DDR_ERR_INT_EN ((volatile uint32_t*)(DDR_BASE + 0xE48)) /* Memory error interrupt enable */ +#define DDR_ERR_SBE ((volatile uint32_t*)(DDR_BASE + 0xE58)) /* Single-Bit ECC memory error management */ + +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */ +#define DDR_SDRAM_CFG_BI 0x00000001 /* Bypass initialization */ +#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */ + +#endif /* NXP_T2080_H */ diff --git a/hal/nxp_t2080.ld b/hal/nxp_t2080.ld index 43e692cab9..65940daee8 100644 --- a/hal/nxp_t2080.ld +++ b/hal/nxp_t2080.ld @@ -13,8 +13,8 @@ MEMORY { FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@ - /* L2 as SRAM - 256KB */ - RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x40000 + /* CPC as SRAM - 1MB */ + RAM (rwx) : ORIGIN = 0xF8F00000, LENGTH = 0x100000 /* DDR - 2GB */ DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index b0fb90b9ab..84b46189f7 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -72,6 +72,21 @@ All TLBs for boot will be in TLB1 and supervisor mode (not user) #include "hal/nxp_ppc.h" +/* e6500 has 64-bit GPRs. When loading 32-bit addresses with bit 31 set + * (addresses >= 0x80000000), the lis instruction sign-extends, putting + * 0xFFFFFFFF in the upper 32 bits. This causes memory access failures. + * Use LOAD_ADDR32 macro to properly load 32-bit addresses on e6500. */ +#ifdef CORE_E6500 +#define LOAD_ADDR32(reg, addr) \ + li reg, 0; \ + oris reg, reg, (addr)@h; \ + ori reg, reg, (addr)@l +#else +#define LOAD_ADDR32(reg, addr) \ + lis reg, (addr)@h; \ + ori reg, reg, (addr)@l +#endif + /* variables from linker script */ .global _start_vector .global isr_empty @@ -194,6 +209,13 @@ startup_init: #ifndef TLB1_NEW_SIZE #define TLB1_NEW_SIZE BOOKE_PAGESZ_256K #endif +/* EPN alignment mask for TLB1_NEW_SIZE page. + * e6500: page = 2^(TSIZE+10), e500/e5500: page = 2^(2*TSIZE+10) */ +#ifdef CORE_E6500 +#define TLB1_EPN_MASK (~((1 << (TLB1_NEW_SIZE + 10)) - 1)) +#else +#define TLB1_EPN_MASK (~((1 << (2 * TLB1_NEW_SIZE + 10)) - 1)) +#endif shrink_default_tlb1: /* Shrink the current TLB1 entry */ bl find_pc @@ -219,12 +241,14 @@ find_pc: oris r3, r3, MAS1_IPROT@h mtspr MAS1, r3 - /* Find page for PC (R1) */ - lis r3, MAS2_EPN@h - ori r3, r3, MAS2_EPN@l + /* Align PC (R1) to TLB page size boundary */ + lis r3, TLB1_EPN_MASK@h + ori r3, r3, TLB1_EPN_MASK@l and r1, r1, r3 /* Set the real and virtual page for this TLB */ + lis r3, MAS2_EPN@h + ori r3, r3, MAS2_EPN@l mfspr r2, MAS2 andc r2, r2, r3 or r2, r2, r1 @@ -267,7 +291,8 @@ find_pc: setup_interrupts: /* Setup interrupt vectors */ - lis r1, (_start_vector)@h + /* e6500 GPRs are 64-bit; avoid sign-extension for high addresses */ + LOAD_ADDR32(r1, _start_vector) mtspr IVPR, r1 /* set the 48-bit high-order prefix address */ #ifdef ENABLE_INTERRUPTS @@ -412,10 +437,17 @@ invalidate_temp_tlb: boot_page: /* make sure we have the default boot page added to MMU */ /* BOOT_PAGE: TLB 1, Entry 0, Supervisor X/R/W, I, TS=0, 4KB, IPROT */ + /* Skip if Entry 0 is the currently executing TLB (R14 from + * shrink_default_tlb1). Overwriting it with a 4K page would unmap + * the code we are running from. The shrink code already set Entry 0 + * to 256K with IPROT, which is sufficient. */ + cmpwi r14, 0 + beq 1f set_tlb(1, 0, BOOT_ROM_ADDR, BOOT_ROM_ADDR, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, 0, BOOKE_PAGESZ_4K, 1, r3); +1: #endif ccsr_tlb: @@ -431,8 +463,7 @@ ccsr_law: #define CCSR_LAW (LAWAR_ENABLE | \ LAWAR_TRGT_ID(LAW_TRGT_CORENET) | \ LAW_SIZE_16MB) - lis r9, CCSRBAR + LAWBAR_BASE(0)@h - ori r9, r9, CCSRBAR + LAWBAR_BASE(0)@l + LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(0)) lis r0, CCSRBAR_PHYS_HIGH@h ori r0, r0, CCSRBAR_PHYS_HIGH@l lis r1, CCSRBAR@h @@ -456,8 +487,7 @@ flash_law: #define FLASH_LAW (LAWAR_ENABLE | \ LAWAR_TRGT_ID(LAW_TRGT_IFC) | \ FLASH_LAW_SIZE) - lis r9, CCSRBAR + LAWBAR_BASE(1)@h - ori r9, r9, CCSRBAR + LAWBAR_BASE(1)@l + LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(1)) lis r0, FLASH_BASE_PHYS_HIGH@h ori r0, r0, FLASH_BASE_PHYS_HIGH@l lis r1, FLASH_BASE_ADDR@h @@ -511,25 +541,33 @@ flash_tlb: #endif /* Map initial DDR, but can be adjusted later in hal_ddr_init() */ - /* DDR - TBL=1, Entry 12/13 */ + /* DDR - TBL=1, Entry 12 (and 13 for e500) */ + #ifdef CORE_E6500 + /* e6500 supports 2GB page size - use single TLB entry */ + set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, 0, + MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, + 0, BOOKE_PAGESZ_2G, 1, r3); + #else + /* e500 uses two 1GB TLB entries */ set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, 0, MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, 0, BOOKE_PAGESZ_1G, 1, r3); - #if DDR_SIZE > 0x40000000 + #if DDR_SIZE > 0x40000000 set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000, 0, MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, 0, BOOKE_PAGESZ_1G, 1, r3); + #endif #endif #endif /* ENABLE_DDR */ #ifdef INITIAL_SRAM_ADDR +#ifndef INITIAL_SRAM_NO_LAW init_sram_law: /* Intial SRAM LAW 2 */ #define INITIAL_SRAM_LAW (LAWAR_ENABLE | \ LAWAR_TRGT_ID(INITIAL_SRAM_LAW_TRGT) | \ INITIAL_SRAM_LAW_SZ) - lis r9, CCSRBAR + LAWBAR_BASE(2)@h - ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l + LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(2)) li r0, 0 /* UPPER=0 */ lis r1, INITIAL_SRAM_ADDR@h ori r1, r1, INITIAL_SRAM_ADDR@l @@ -542,9 +580,12 @@ init_sram_law: /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */ lwz r2, 8(r9) isync +#endif /* !INITIAL_SRAM_NO_LAW */ init_sram_tlb: - /* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT */ + /* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT + * CPC SRAM uses cacheable memory-coherent (M) access. + * SRAM is zeroed via dcbz to avoid reading uninitialized ECC data. */ set_tlb(1, 9, INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, @@ -556,31 +597,31 @@ init_sram_tlb: #if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */ #ifdef L2SRAM_ADDR l2_setup_sram: - /* T2080RM: 8.4.2.2 or T1024RM 13.4.2.2 - * Enabling the CPC after Power-On Reset */ + /* T2080RM: 8.4.2.2 - CPC initialization + * Restored working configuration from pre-T1024 codebase: + * Configure SRAM control registers, then enable CPC with parity. + * The LAW (DDR_1) provides CoreNet routing; CPC intercepts before DDR. + * SRAM is zeroed later via dcbz through cacheable TLB (MAS2_M). */ /* R1 = CPC base */ - lis r1, CPC_BASE@h - ori r1, r1, CPC_BASE@l + LOAD_ADDR32(r1, CPC_BASE) - /* Set CPC SRAM control register */ - /* SRAM high addrress 0x0 */ + /* Configure CPC SRAM control registers */ li r0, 0 - stw r0, CPCSRCR1(r1) - /* SRAM low address */ - lis r0, L2SRAM_ADDR@h - ori r0, r0, L2SRAM_ADDR@l + stw r0, CPCSRCR1(r1) /* SRAM high address = 0 */ + /* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */ + LOAD_ADDR32(r0, L2SRAM_ADDR) /* Enable SRAM and set size (must match L2SRAM_SIZE) */ - ori r0, r0, (CPCSRCR0_SRAMSZ_256 | CPCSRCR0_SRAMEN) + ori r0, r0, (CPCSRCR0_SRAMSZ_1024 | CPCSRCR0_SRAMEN) stw r0, CPCSRCR0(r1) - /* Enable memory mapped SRAM */ - lis r0, CPCCSR0_SRAM_ENABLE@h + /* Enable CPC with parity */ + lis r0, (CPCCSR0_CPCE | CPCCSR0_CPCPE)@h mbar isync stw r0, CPCCSR0(r1) mbar - /* Disable speculation */ + /* Disable speculation (Errata A-006593) */ lwz r0, CPCHDBCR0(r1) oris r0, r0, CPCHDBCR0_SPEC_DIS@h stw r0, CPCHDBCR0(r1) @@ -590,15 +631,15 @@ l2_setup_sram: l2_setup_cache: /* E6500CORERM: 11.7 L2 cache state */ /* R5 = L2 cluster 1 base */ - lis r5, L2_CLUSTER_BASE(0)@h - ori r5, r5, L2_CLUSTER_BASE(0)@l - /* Invalidate and clear locks */ - lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h - ori r1, r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@l + LOAD_ADDR32(r5, L2_CLUSTER_BASE(0)) + + /* Flash invalidate L2 (locks already clear after reset) */ + lis r1, L2CSR0_L2FI@h + ori r1, r1, L2CSR0_L2FI@l sync stw r1, L2CSR0(r5) - /* poll till invalidate and lock bits are cleared */ + /* Poll until L2FI clears */ l2_poll_invclear: lwz r4, L2CSR0(r5) and. r4, r1, r4 @@ -612,7 +653,7 @@ l2_poll_invclear: /* enable L2 with parity */ sync isync - lis r4, (L2CSR0_L2E | L2CSR0_L2PE)@h + LOAD_ADDR32(r4, (L2CSR0_L2E | L2CSR0_L2PE)) stw r4, L2CSR0(r5) isync @@ -713,10 +754,9 @@ l1_tlb: #endif #endif /* ENABLE_L1_CACHE */ -#ifdef CACHE_SRAM_ADDR +#ifdef L1_CACHE_ADDR cache_sram_init: - lis r3, CACHE_SRAM_ADDR@h - ori r3, r3, CACHE_SRAM_ADDR@l + LOAD_ADDR32(r3, L1_CACHE_ADDR) /* read the cache size */ mfspr r2, L1CFG0 andi. r2, r2, 0x1FF @@ -736,13 +776,25 @@ cache_sram_init_loop: #endif addi r3, r3, CACHE_LINE_SIZE bdnz cache_sram_init_loop -#endif /* CACHE_SRAM_ADDR */ +#elif defined(L2SRAM_ADDR) +cache_sram_init: + /* Zero CPC SRAM via cache (MAS2_M = cacheable, memory coherent). + * dcbz allocates zeroed cache lines without reading from CPC, + * avoiding ECC/parity issues from uninitialized SRAM. */ + LOAD_ADDR32(r3, L2SRAM_ADDR) + li r0, 0 + LOAD_ADDR32(r2, (L2SRAM_SIZE / CACHE_LINE_SIZE)) + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, CACHE_LINE_SIZE + bdnz 1b +#endif /* L1_CACHE_ADDR */ setup_stack: /* Build top of stack address */ /* Reserve 64 bytes of initial data (must be 16 byte aligned) */ - lis r1, (_end_stack-64)@h - ori r1, r1, (_end_stack-64)@l + LOAD_ADDR32(r1, _end_stack-64) /* PowerPC e500 Application Binary Interface User's Guide * 2.3.5.1.1 Minimal Stack Frame: No Local Variables or Saved Parameters @@ -882,7 +934,7 @@ dcache_disable: lis r4, 0 ori r4, r4, L1CSR_CE andc r3, r3, r4 - mtspr L1CSR0, r0 + mtspr L1CSR0, r3 isync blr #endif @@ -996,8 +1048,29 @@ in_ram: .section .isr_vector .align 8 isr_empty: - nop - rfi + /* Minimal fault dump for early bring-up */ +#ifdef L2SRAM_ADDR + LOAD_ADDR32(r0, L2SRAM_ADDR) + addi r0, r0, 0x200 + mfspr r1, SRR0 + stw r1, 0x00(r0) + mfspr r1, SRR1 + stw r1, 0x04(r0) + mfspr r1, SPRN_ESR + stw r1, 0x08(r0) + mfspr r1, SPRN_DEAR + stw r1, 0x0C(r0) + mfspr r1, SPRN_MCSR + stw r1, 0x10(r0) + mfspr r1, SPRN_PIR + stw r1, 0x14(r0) + /* Machine check exceptions use MCSRR0/MCSRR1 (not SRR0/SRR1) */ + mfspr r1, SPRN_MCSRR0 + stw r1, 0x18(r0) + mfspr r1, SPRN_MCSRR1 + stw r1, 0x1C(r0) +#endif +1: b 1b #endif /* reset entry point - must be at end of .S */