From 637267807f09ed4994cf93dd76aedce21c2f4e02 Mon Sep 17 00:00:00 2001 From: Bao Nguyen Date: Mon, 23 Feb 2026 17:47:12 -0500 Subject: [PATCH] docs(dn): Bao Nguyen 2/23/26 --- src/design_notebooks/2026spring/bln7876.md | 39 ++++++++++++++++++---- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/src/design_notebooks/2026spring/bln7876.md b/src/design_notebooks/2026spring/bln7876.md index 2e434547..d2145750 100644 --- a/src/design_notebooks/2026spring/bln7876.md +++ b/src/design_notebooks/2026spring/bln7876.md @@ -1,12 +1,37 @@ # Bao's Design Notebook ## Week of January 26th - -### Team's meeting -* First team meeting on January 28th. -* Familiarize myself with the VIP's syllabus. -* Partnered up with Tim to start the RISC-16 onboarding project. +### Team Meeting +* January 28th: I attended the first team meeting on campus. +* I familiarized myself with the VIP's syllabus. +* I examined the RiSC-16's [sequential implementation](https://user.eng.umd.edu/~blj/RiSC/RiSC-seq.pdf) and [instruction-set architecture](https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf). +* I partnered up with [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) to start the RiSC-16 onboarding project. + * We set weekly meeting time at 2 P.M. every Monday. ## Week of February 2nd -* Created Github repo of the RISC-16 onboarding project and shared it with Noah. -* Finished the first two modules (Assignment 1) of the onboarding project, collaborating with Tim using Live Share extension on Virtual Studio Code. +### RiSC-16 Onboarding Project +* A Github repo of the RiSC-16 onboarding project was created and shared with [Noah](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/nm4207.md). +* February 7th: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I finished the two modules of Assignment 2 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code. + * We implemented the instruction memory and program counter. + * Flu-like viral infection restricted me and [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) from meeting at intended time. + +## Week of February 9th +### RiSC-16 Onboarding Project +* February 10th and February 11th: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I finished the two modules of Assignment 2 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code. + * We implemented the arithmetic logic unit (ALU) and data memory. + * Post-illness fatigue restricted me and [Tim] from finishing the assignment in one meeting, so we splitted into two meetings. + +## Week of February 16th +### RiSC-16 Onboarding Project +* February 16th and February 18th: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I finished the two modules of Assignment 3 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code. + * We implemented the register file and control. We also ensured every positive clock edge write to the correct location in memory. + * We were able to meet at the intended time; however, time constraints and conflicts necessitate to finish this in two separate meetings. +### Team Meeting +* February 18th: I attended the second team meeting on Zoom due to delaying MTA trains. + +## Week of February 23rd +* February 23rd: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I finished the module of Assignment 4 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code. + * We implemented the ALU testbench. We also wondered whether a dedicated folder should be created for testbenches. + * Another module (Sixth RiSC-16 Module: +Control Module) of the onboarding project was included in the assignment slides, ofwhich not much information was shared. We henceforth decided not to accomplish it for now. + * We were able to meet at the intended time. \ No newline at end of file